The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved large scale integration CMOS semiconductor devices.
Semiconductor chips are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate and separated therefrom by a gate insulator. Source and drain regions are then formed in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. This generally-described structure cooperates to function as a transistor.
To promote the proper functioning of the transistor by establishing an electrical contact point to,a source or drain of a transistor, a layer of silicide such as Titanium disilicide (TiSi2) is formed on the substrate adjacent the gate. As recognized by the present invention, however, it can be difficult to form the silicide on heavily doped regions, particularly in N-channel transistors that use Arsenic as the dopant, Indeed, silicide formation is retarded on regions that have been heavily doped with Arsenic, degrading circuit speed vis-a-vis transistors that have properly formed silicides. The present invention recognizes the above problem and provides the solutions noted herein.
A method is disclosed for making a semiconductor device, particularly but not limited to an N-channel metal oxide silicon field effect transistor (MOSFET). The method includes implanting a dopant into a substrate having a surface to establish a dopant implant profile defining a peak. In accordance with the present invention, the peak is distanced from the surface. The dopant is then activated.
In a preferred embodiment, to establish a dopant concentration profile having a peak distanced from the surface of the substrate, the dopant is implanted using an implant energy of at least ten thousand electron volts (10 KeV) Moreover, to define an active region lower boundary, a preamorphization substance is implanted into the substrate prior to activating the dopant. The preferred method includes activating the dopant using relatively low temperature rapid thermal annealing, i.e., a temperature of no more than six hundred fifty degrees Celsius (650xc2x0 C.), to confine the activated region to be between the surface of the substrate and the active region lower boundary. With the relatively deep dopant concentration peak, a silicide can be established on the surface of the substrate with silicide retardation effects being suppressed.
In another aspect, a semiconductor device includes a substrate defining a surface, and an activated region in the substrate the activated region includes Arsenic implanted to a predetermined depth in the substrate, with the Arsenic defining a concentration profile from the surface to the predetermined depth. In accordance with present principles, the profile has a peak that is spaced from the surface of the substrate.
In still another aspect, a method for making a CMOS device includes providing a substrate defining a surface, and implanting a dopant into the substrate such that the highest concentration of dopant is spaced from the surface. The method also includes establishing a silicide on the surface. As disclosed in further detail below, the establishing act is promoted by the spacing of the highest concentration of dopant from the surface.
Other features of the present invention are disclosed or apparent in the section entitled xe2x80x9cDETAILED DESCRIPTION OF THE INVENTIONxe2x80x9d.